ALAAN; Urusa

Patent Applications and Registrations

Patent applications and USPTO patent grants for ALAAN; Urusa.The latest application filed is for "novel esd protection decoupled from diffusion".

Company Profile

11.4.22

ALAAN; Urusa - Hillsboro OR
Alaan; Urusa - Hilsboro OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Compositional Engineering Of Schottky Diode App 20220199839 - SEN GUPTA; Arnab ; et al.	2022-06-23
Novel Esd Protection Decoupled From Diffusion App 20220199609 - ALAAN; Urusa ; et al.	2022-06-23
Novel Method To Form Single Crystal Mosfet And Fefet App 20220199801 - MAJHI; Prashant ; et al.	2022-06-23
Integrated Circuits and Methods for Forming Thin Film Crystal Layers App 20220148917 - NAYLOR; Carl ; et al.	2022-05-12
Damascene Interconnect Structures With Low Resistance Vias For Integrated Circuits App 20220102268 - Alaan; Urusa ; et al.	2022-03-31
Integrated circuits and methods for forming thin film crystal layers Grant 11,276,644 - Naylor , et al. March 15, 2	2022-03-15
Transistor Channel Passivation With 2d Crystalline Material App 20220059702 - Naylor; Carl ; et al.	2022-02-24
Stacked Forksheet Transistors App 20210407999 - HUANG; Cheng-Ying ; et al.	2021-12-30
Integrated Circuits And Methods For Forming Integrated Circuits App 20210351105 - Naylor; Carl ; et al.	2021-11-11
Transistor channel passivation with 2D crystalline material Grant 11,171,239 - Naylor , et al. November 9, 2	2021-11-09
Integrated circuits and methods for forming integrated circuits Grant 11,164,809 - Naylor , et al. November 2, 2	2021-11-02
Gate-all-around Integrated Circuit Structures Having Fin Stack Isolation App 20210305430 - GULER; Leonard P. ; et al.	2021-09-30
Integrated circuits and methods for forming integrated circuits Grant 11,018,075 - Naylor , et al. May 25, 2	2021-05-25
Integrated Circuit Structures Having Linerless Self-forming Barriers App 20210090991 - SHARMA; Abhishek A. ; et al.	2021-03-25
Transistor Channel Passivation With 2d Crystalline Material App 20210083122 - Naylor; Carl ; et al.	2021-03-18
Device With Air-gaps To Reduce Coupling Capacitance And Process For Forming Such App 20200411526 - SHARMA; Abhishek ; et al.	2020-12-31
Vertically Stacked Memory Elements With Air Gap App 20200403033 - Lilak; Aaron D. ; et al.	2020-12-24
Transistors With Metal Chalcogenide Channel Materials App 20200388685 - Sharma; Abhishek A. ; et al.	2020-12-10
Local Interconnect With Air Gap App 20200388565 - Lin; Kevin L. ; et al.	2020-12-10
Non-planar Transistors With Channel Regions Having Varying Widths App 20200295002 - Snyder; Stephen D. ; et al.	2020-09-17
Selectable Vias For Back End Of Line Interconnects App 20200219804 - Jezewski; Christopher ; et al.	2020-07-09
Integrated circuits and methods for forming integrated circuits App 20200194338 - NAYLOR; Carl ; et al.	2020-06-18
Integrated circuits and methods for forming thin film crystal layers App 20200194376 - NAYLOR; Carl ; et al.	2020-06-18
Adhesion Structure For Thin Film Transistor App 20200185532 - Lin; Kevin ; et al.	2020-06-11
Diode Based Resistive Random Access Memory App 20200098824 - SHARMA; Abhishek ; et al.	2020-03-26

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