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Hardware-Assisted Memory Disaggregation with Recovery from Network Failures Using Non-Volatile Memory
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Low Latency Inter-chip Communication Mechanism In A Multi-chip Processing System
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Methods and systems for distributing memory requests
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Low latency inter-chip communication mechanism in multi-chip processing system
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Systems And Methods For Allowing Flexible Chip Configuration By External Entity
App 20200252434 - Kind Code | 2020-08-06 |
Low Latency Inter-chip Communication Mechanism In Multi-chip Processing System
App 20200250088 - Kind Code | 2020-08-06 |
Methods And Systems For Distributing Memory Requests
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Systems and methods for allowing flexible chip configuration by external entity while maintaining secured boot environment
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Methods and systems for distributing memory requests
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Method and apparatus for determining metric for selective caching
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Verification of a multichip coherence protocol
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Method And Apparatus For Determining Metric For Selective Caching
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Design And Verification Of A Multichip Coherence Protocol
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Inter-chip interconnect protocol for a multi-chip system
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System and method for automated functional coverage generation and management for IC design protocols
Grant 9,355,206 - Ikram , et al. May 31, 2 | 2016-05-31 |
Systems And Methods For Allowing Flexible Chip Configuration By External Entity While Maintaining Secured Boot Environment
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Systems And Methods For Automated Functional Coverage Generation And Management For Ic Design Protocols
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Inter-chip Interconnect Protocol For A Multi-chip System
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Multi-core Network Processor Interconnect With Multi-node Connection
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Systems and methods for specifying. modeling, implementing and verifying IC design protocols
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Systems And Methods For Specifying. Modeling, Implementing And Verifying Ic Design Protocols
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Node identification for distributed shared memory system
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DMA in Distributed Shared Memory System
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Block Caching for Cache-Coherent Distributed Shared Memory
App 20110004729 - Akkawi; Isam ; et al. | 2011-01-06 |
Node Identification for Distributed Shared Memory System
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Virtual input/output server
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Node identification for distributed shared memory system
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Fast invalidation for cache coherency in distributed shared memory system
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