Akarvardar; Murat K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Akarvardar; Murat K..The latest application filed is for "bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide".

Company Profile

1.7.7

Akarvardar; Murat K. - Saratoga Springs NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vertical field effect transistor formation with critical dimension control Grant 10,217,846 - Xie , et al. Feb	2019-02-26
Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide Grant 9,842,897 - Akarvardar , et al. December 12, 2	2017-12-12
Bulk Finfet With Partial Dielectric Isolation Featuring A Punch-through Stopping Layer Under The Oxide App 20160284802 - Akarvardar; Murat K. ; et al.	2016-09-29
Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide Grant 9,385,233 - Akarvardar , et al. July 5, 2	2016-07-05
Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device Grant 9,293,587 - Jacob , et al. March 22, 2	2016-03-22
Method for single fin cuts using selective ion implants Grant 9,287,130 - Cai , et al. March 15, 2	2016-03-15
Methods Of Forming Metastable Replacement Fins For A Finfet Semiconductor Device By Performing A Replacement Growth Process App 20160064250 - Jacob; Ajey P. ; et al.	2016-03-03
Methods of forming replacement fins for a FinFET semiconductor device by performing a replacement growth process Grant 9,240,342 - Jacob , et al. January 19, 2	2016-01-19
Undoped Epitaxial Layer For Junction Isolation In A Fin Field Effect Transistor (finfet) Device App 20150137237 - Jacob; Ajey Poovannummoottil ; et al.	2015-05-21
Device isolation in finFET CMOS Grant 8,963,259 - Jacob , et al. February 24, 2	2015-02-24
Forming Embedded Source And Drain Regions To Prevent Bottom Leakage In A Dielectrically Isolated Fin Field Effect Transistor (finfet) Device App 20150028348 - Jacob; Ajey Poovannummoottil ; et al.	2015-01-29
Methods Of Forming Replacement Fins For A Finfet Semiconductor Device By Performing A Replacement Growth Process App 20150024573 - Jacob; Ajey P. ; et al.	2015-01-22
Bulk Finfet With Partial Dielectric Isolation Featuring A Punch-through Stopping Layer Under The Oxide App 20150001591 - Akarvardar; Murat K. ; et al.	2015-01-01
Device Isolation In Finfet Cmos App 20140353801 - Jacob; Ajey P. ; et al.	2014-12-04

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