Ajuria; Sergio A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ajuria; Sergio A..The latest application filed is for "semiconductor package with embedded capacitor and methods of manufacturing same".

Company Profile

3.13.11

Ajuria; Sergio A. - Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor manufacturing using disposable test circuitry within scribe lanes Grant 10,553,508 - Reber , et al. Fe	2020-02-04
Semiconductor package with embedded capacitor and methods of manufacturing same Grant 10,522,615 - Ajuria , et al. Dec	2019-12-31
Semiconductor Package With Embedded Capacitor And Methods Of Manufacturing Same App 20170084682 - AJURIA; SERGIO A. ; et al.	2017-03-23
Semiconductor manufacturing for forming bond pads and seal rings Grant 9,601,354 - Reber , et al. March 21, 2	2017-03-21
Semiconductor package with embedded capacitor and methods of manufacturing same Grant 9,548,266 - Ajuria , et al. January 17, 2	2017-01-17
Semiconductor Manufacturing For Forming Bond Pads And Seal Rings App 20160064294 - REBER; DOUGLAS M. ; et al.	2016-03-03
Semiconductor Package With Embedded Capacitor And Methods Of Manufacturing Same App 20160064324 - Ajuria; Sergio A. ; et al.	2016-03-03
Method for forming a packaged semiconductor device Grant 9,134,366 - Ajuria , et al. September 15, 2	2015-09-15
Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes App 20150200146 - Reber; Douglas M. ; et al.	2015-07-16
Method For Forming A Packaged Semiconductor Device App 20150061709 - Ajuria; Sergio A. ; et al.	2015-03-05
Package level ESD protection and method therefor Grant 8,059,380 - Ajuria , et al. November 15, 2	2011-11-15
Package Level Esd Protection And Method Therefor App 20090284881 - Ajuria; Sergio A. ; et al.	2009-11-19
Probe pad arrangement for an integrated circuit and method of forming App 20060022353 - Ajuria; Sergio A. ; et al.	2006-02-02
Combined trench isolation and inlaid process for integrated circuit formation Grant 5,963,818 - Kao , et al. October 5, 1	1999-10-05
Method for forming a semiconductor device having a nitrided oxide dielectric layer Grant 5,885,870 - Maiti , et al. March 23, 1	1999-03-23
Method of forming a semiconductor structure having an air region Grant 5,324,683 - Fitch , et al. June 28, 1	1994-06-28

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