Aipperspach; Anthony Gus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Aipperspach; Anthony Gus.The latest application filed is for "implementing precise resistance measurement for 2d array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor".

Company Profile

0.34.31

Aipperspach; Anthony Gus - Rochester MN
Aipperspach, Anthony Gus - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor Grant 7,764,531 - Aipperspach , et al. July 27, 2	2010-07-27
Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse Grant 7,733,722 - Aipperspach , et al. June 8, 2	2010-06-08
Method and circuit for implementing enhanced eFuse sense circuit Grant 7,729,188 - Aipperspach , et al. June 1, 2	2010-06-01
Method and circuit for implementing eFuse sense amplifier verification Grant 7,725,844 - Aipperspach , et al. May 25, 2	2010-05-25
Implementing Efuse sense amplifier testing without blowing the Efuse Grant 7,689,950 - Aipperspach , et al. March 30, 2	2010-03-30
Implementing Precise Resistance Measurement for 2D Array Efuse Bit Cell Using Differential Sense Amplifier, Balanced Bitlines, and Programmable Reference Resistor App 20100067319 - Aipperspach; Anthony Gus ; et al.	2010-03-18
Method and Circuit for Implementing Efuse Resistance Screening App 20090212850 - Aipperspach; Anthony Gus ; et al.	2009-08-27
Method and Circuit for Implementing Enhanced Efuse Sense Circuit App 20090201756 - Aipperspach; Anthony Gus ; et al.	2009-08-13
Method and Circuit for Implementing Efuse Sense Amplifier Verification App 20090201074 - Aipperspach; Anthony Gus ; et al.	2009-08-13
Apparatus For Implementing Efuse Sense Amplifier Testing Without Blowing The Efuse App 20090175106 - Aipperspach; Anthony Gus ; et al.	2009-07-09
Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells Grant 7,535,750 - Wagner , et al. May 19, 2	2009-05-19
Electrically programmable fuse sense circuit Grant 7,532,057 - Aipperspach , et al. May 12, 2	2009-05-12
Electrically programmable fuse sense circuit Grant 7,528,646 - Aipperspach , et al. May 5, 2	2009-05-05
Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration App 20090063921 - Aipperspach; Anthony Gus ; et al.	2009-03-05
Method for implementing eFuse sense amplifier testing without blowing the eFuse Grant 7,489,572 - Aipperspach , et al. February 10, 2	2009-02-10
Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays App 20080212396 - Adams; Chad Allen ; et al.	2008-09-04
Method and Apparatus for Implementing Efuse Sense Amplifier Testing Without Blowing the Efuse App 20080170449 - Aipperspach; Anthony Gus ; et al.	2008-07-17
Method and Apparatus for Implementing Efuse Sense Amplifier Testing Without Blowing the Efuse App 20080169843 - Aipperspach; Anthony Gus ; et al.	2008-07-17
Delay mechanism for unbalanced read/write paths in domino SRAM arrays Grant 7,400,550 - Adams , et al. July 15, 2	2008-07-15
Electrically Programmable Fuse Sense Circuit App 20080157851 - Aipperspach; Anthony Gus ; et al.	2008-07-03
Delay Mechanism For Unbalanced Read/write Paths In Domino Sram Arrays App 20080117695 - Adams; Chad Allen ; et al.	2008-05-22
Electrically Programmable Fuse Sense Circuit App 20080106323 - Aipperspach; Anthony Gus ; et al.	2008-05-08
Pulse-width limited chip clock design Grant 7,318,209 - Aipperspach , et al. January 8, 2	2008-01-08
Methods and apparatus for accessing memory Grant 7,289,370 - Adams , et al. October 30, 2	2007-10-30
Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmetrical Memory Cells And A Method To Operate Such A Memory App 20070165447 - Wagner; Otto ; et al.	2007-07-19
Simplified method for limiting clock pulse width Grant 7,242,233 - Aipperspach , et al. July 10, 2	2007-07-10
Array redundancy supporting multiple independent repairs Grant 7,206,236 - Aipperspach , et al. April 17, 2	2007-04-17
Methods and apparatus for accessing memory App 20070019461 - Adams; Chad Allen ; et al.	2007-01-25
Dynamic latching logic structure with static interfaces for implementing improved data setup time Grant 7,161,390 - Aipperspach , et al. January 9, 2	2007-01-09
Method and apparatus for reducing time delay through static bitlines of a static memory App 20060245240 - Aipperspach; Anthony Gus ; et al.	2006-11-02
Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activity Grant 7,092,281 - Aipperspach , et al. August 15, 2	2006-08-15
Method and apparatus to reduce bias temperature instability (BTI) effects Grant 7,009,905 - Aipperspach , et al. March 7, 2	2006-03-07
Dynamic latching logic structure with static interfaces for implementing improved data setup time App 20060044020 - Aipperspach; Anthony Gus ; et al.	2006-03-02
Read/write methods for limited memory access applications App 20060023552 - Aipperspach; Anthony Gus ; et al.	2006-02-02
Method and apparatus to reduce bias temperature instability (BTI) effects App 20050134360 - Aipperspach, Anthony Gus ; et al.	2005-06-23
Lower power and reduced device split local and continuous bitline for domino read SRAMs Grant 6,901,003 - Adams , et al. May 31, 2	2005-05-31
Simplified method for limiting clock pulse width App 20050091620 - Aipperspach, Anthony Gus ; et al.	2005-04-28
Lower power and reduced device split local and continuous bitline for domino read SRAMs App 20050007813 - Adams, Chad Allen ; et al.	2005-01-13
Pulse-width limited chip clock design App 20050010885 - Aipperspach, Anthony Gus ; et al.	2005-01-13
SOI sense amplifier method and apparatus Grant 6,833,737 - Aipperspach December 21, 2	2004-12-21
SOI sense amplifier method and apparatus App 20040150470 - Aipperspach, Anthony Gus	2004-08-05
Compact SRAM cell layout for implementing one-port or two-port operation Grant 6,737,685 - Aipperspach , et al. May 18, 2	2004-05-18
Multiple mode elastic data transfer interface Grant 6,661,726 - Aipperspach , et al. December 9, 2	2003-12-09
Split local and continuous bitline for fast domino read SRAM Grant 6,657,886 - Adams , et al. December 2, 2	2003-12-02
Split Local And Continuous Bitline For Fast Domino Read Sram App 20030210565 - Adams, Chad Allen ; et al.	2003-11-13
Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test Grant 6,643,804 - Aipperspach , et al. November 4, 2	2003-11-04
Master-slave latch circuit for multithreaded processing App 20030200424 - Aipperspach, Anthony Gus ; et al.	2003-10-23
SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies Grant 6,635,518 - Aipperspach , et al. October 21, 2	2003-10-21
Master-slave latch circuit for multithreaded processing Grant 6,629,236 - Aipperspach , et al. September 30, 2	2003-09-30
Compact SRAM cell layout for implementing one-port or two-port operation App 20030133322 - Aipperspach, Anthony Gus ; et al.	2003-07-17
Multiple mode elastic data transfer interface App 20030128611 - Aipperspach, Anthony Gus ; et al.	2003-07-10
Silicon-on-insulator SRAM cells with increased stability and yield App 20030123279 - Aipperspach, Anthony Gus ; et al.	2003-07-03
Method And Ring Oscillator For Evaluating Dynamic Circuits App 20030071692 - Aipperspach, Anthony Gus ; et al.	2003-04-17
Silicon-on-insulator SRAM cells with increased stability and yield App 20030058675 - Aipperspach, Anthony Gus ; et al.	2003-03-27
SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies App 20020145174 - Aipperspach, Anthony Gus ; et al.	2002-10-10
Laser fuseblow protection method for silicon on insulator (SOI) transistors App 20020027248 - Aipperspach, Anthony Gus ; et al.	2002-03-07
SRAM that can be clocked on either clock phase Grant 6,260,164 - Aipperspach , et al. July 10, 2	2001-07-10
Method and apparatus for assembling array and datapath macros Grant 6,247,166 - Aipperspach , et al. June 12, 2	2001-06-12
Apparatus and method for efficiently correcting defects in memory circuits Grant 6,205,063 - Aipperspach , et al. March 20, 2	2001-03-20
Dynamic repair of redundant memory array Grant 6,181,614 - Aipperspach , et al. January 30, 2	2001-01-30
Low power wordline decoder circuit with minimized hold time Grant 6,172,531 - Aipperspach , et al. January 9, 2	2001-01-09
Write multiplexer apparatus and method for multiple write port programmable memory Grant 5,991,208 - Aipperspach , et al. November 23, 1	1999-11-23
Global wire management apparatus and method for a multiple-port random access memory Grant 5,991,224 - Aipperspach , et al. November 23, 1	1999-11-23
Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme Grant 5,835,502 - Aipperspach , et al. November 10, 1	1998-11-10
Multi-threaded cell for a memory Grant 5,778,243 - Aipperspach , et al. July 7, 1	1998-07-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.