Ahmed; Shibly S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ahmed; Shibly S..The latest application filed is for "low power power-up reset output driver".

Company Profile

0.46.15

Ahmed; Shibly S. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low power power-up reset output driver Grant 11,368,155 - Tran , et al. June 21, 2	2022-06-21
Low Power Power-up Reset Output Driver App 20220182058 - Tran; Dzung T. ; et al.	2022-06-09
Controlling the latchup effect Grant 9,759,764 - Lin , et al. September 12, 2	2017-09-12
Controlling the latchup effect Grant 8,912,014 - Lin , et al. December 16, 2	2014-12-16
Junction leakage suppression in memory devices Grant 8,536,011 - Ahmed , et al. September 17, 2	2013-09-17
Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin Grant 8,217,450 - Yu , et al. July 10, 2	2012-07-10
Junction Leakage Suppression In Memory Devices App 20110176363 - AHMED; Shibly S. ; et al.	2011-07-21
Junction leakage suppression in memory devices Grant 7,939,440 - Ahmed , et al. May 10, 2	2011-05-10
Reversed T-shaped finfet Grant 7,541,267 - Wang , et al. June 2, 2	2009-06-02
Systems and methods for forming multiple fin structures using metal-induced-crystallization Grant 7,498,225 - Wang , et al. March 3, 2	2009-03-03
Formation of semiconductor devices to achieve <100> channel orientation Grant 7,432,558 - Ahmed , et al. October 7, 2	2008-10-07
Selective channel implantation for forming semiconductor devices with different threshold voltages Grant 7,262,104 - Wang , et al. August 28, 2	2007-08-28
Double gate semiconductor device having a metal gate Grant 7,256,455 - Ahmed , et al. August 14, 2	2007-08-14
Reversed T-shaped FinFET Grant 7,250,645 - Wang , et al. July 31, 2	2007-07-31
Junction leakage suppression in memory devices App 20070052002 - Ahmed; Shibly S. ; et al.	2007-03-08
Narrow-body damascene tri-gate FinFET Grant 7,186,599 - Ahmed , et al. March 6, 2	2007-03-06
Method of manufacturing a semiconductor device having a fin structure Grant 7,179,692 - Yu , et al. February 20, 2	2007-02-20
Multi-step chemical mechanical polishing of a gate area in a FinFET Grant 7,125,776 - Achuthan , et al. October 24, 2	2006-10-24
Varying carrier mobility in semiconductor devices to achieve overall design goals Grant 7,095,065 - Yu , et al. August 22, 2	2006-08-22
Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices Grant 7,091,068 - Ahmed , et al. August 15, 2	2006-08-15
Sacrificial oxide for minimizing box undercut in damascene FinFET Grant 7,084,018 - Ahmed , et al. August 1, 2	2006-08-01
Damascene tri-gate FinFET Grant 7,041,542 - Ahmed , et al. May 9, 2	2006-05-09
Narrow body raised source/drain metal gate MOSFET Grant 7,034,361 - Yu , et al. April 25, 2	2006-04-25
Source and drain protection and stringer-free gate formation in semiconductor devices Grant 7,029,959 - Yang , et al. April 18, 2	2006-04-18
Self aligned damascene gate Grant 7,029,958 - Tabery , et al. April 18, 2	2006-04-18
Method for forming a tri-gate MOSFET Grant 6,998,301 - Yu , et al. February 14, 2	2006-02-14
Semiconductor device with fully silicided source/drain and damascence metal gate Grant 6,995,438 - Ahmed , et al. February 7, 2	2006-02-07
Dual silicon layer for chemical mechanical polishing planarization Grant 6,982,464 - Achuthan , et al. January 3, 2	2006-01-03
Isolated FinFET P-channel/N-channel transistor pair Grant 6,974,983 - Hill , et al. December 13, 2	2005-12-13
Damascene gate semiconductor processing with local thinning of channel region Grant 6,967,175 - Ahmed , et al. November 22, 2	2005-11-22
Semiconductor device having a gate structure surrounding a fin Grant 6,960,804 - Yang , et al. November 1, 2	2005-11-01
Non-volatile memory device Grant 6,958,512 - Wu , et al. October 25, 2	2005-10-25
Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages Grant 6,936,882 - Ahmed , et al. August 30, 2	2005-08-30
Damascene tri-gate FinFET App 20050153492 - Ahmed, Shibly S. ; et al.	2005-07-14
Narrow-body damascene tri-gate FinFET App 20050153485 - Ahmed, Shibly S. ; et al.	2005-07-14
Merged FinFET P-channel/N-channel pair Grant 6,914,277 - Hill , et al. July 5, 2	2005-07-05
Multi-step chemical mechanical polishing of a gate area in a FinFET App 20050118824 - Achuthan, Krishnashree ; et al.	2005-06-02
Self aligned damascene gate App 20050104091 - Tabery, Cyrus E. ; et al.	2005-05-19
System and method for forming stacked fin structure using metal-induced-crystallization Grant 6,894,337 - Wang , et al. May 17, 2	2005-05-17
Additional gate control for a double-gate MOSFET Grant 6,876,042 - Yu , et al. April 5, 2	2005-04-05
Dual silicon layer for chemical mechanical polishing planarization App 20050056845 - Achuthan, Krishnashree ; et al.	2005-03-17
Multi-step chemical mechanical polishing of a gate area in a FinFET Grant 6,855,607 - Achuthan , et al. February 15, 2	2005-02-15
Damascene finfet gate with selective metal interdiffusion Grant 6,855,989 - Wang , et al. February 15, 2	2005-02-15
Varying Carrier Mobility In Semiconductor Devices To Achieve Overall Design Goals App 20050029603 - Yu, Bin ; et al.	2005-02-10
Method of manufacturing a semiconductor device having a U-shaped gate structure App 20050006666 - Yu, Bin ; et al.	2005-01-13
Semiconductor device having a U-shaped gate structure Grant 6,833,588 - Yu , et al. December 21, 2	2004-12-21
Multi-step Chemical Mechanical Polishing Of A Gate Area In A Finfet App 20040253775 - Achuthan, Krishnashree ; et al.	2004-12-16
Narrow fins by oxidation in double-gate finfet Grant 6,812,119 - Ahmed , et al. November 2, 2	2004-11-02
Dual silicon layer for chemical mechanical polishing planarization Grant 6,812,076 - Achuthan , et al. November 2, 2	2004-11-02
Systems and methods for forming dense n-channel and p-channel fins using shadow implanting Grant 6,787,406 - Hill , et al. September 7, 2	2004-09-07
Method for forming a fin in a finFET device Grant 6,787,854 - Yang , et al. September 7, 2	2004-09-07
Method using planarizing gate material to improve gate critical dimension in semiconductor devices Grant 6,787,439 - Ahmed , et al. September 7, 2	2004-09-07
Double gate semiconductor device having separate gates App 20040126975 - Ahmed, Shibly S. ; et al.	2004-07-01
Dual silicon layer for chemical mechanical polishing planarization Grant 6,756,643 - Achuthan , et al. June 29, 2	2004-06-29
Double gate semiconductor device having a metal gate App 20040110097 - Ahmed, Shibly S. ; et al.	2004-06-10
Planarizing gate material to improve gate critical dimension in semiconductor devices App 20040092062 - Ahmed, Shibly S. ; et al.	2004-05-13
Semiconductor device having a U-shaped gate structure App 20040075121 - Yu, Bin ; et al.	2004-04-22
Damascene gate process with sacrificial oxide in semiconductor devices Grant 6,686,231 - Ahmed , et al. February 3, 2	2004-02-03
Double gate semiconductor device having separate gates Grant 6,611,029 - Ahmed , et al. August 26, 2	2003-08-26