Agrawal; Vishwani D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Agrawal; Vishwani D..The latest application filed is for "system and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuits".

Company Profile

0.7.1

Agrawal; Vishwani D. - Auburn AL
Agrawal; Vishwani D. - New Providence NJ
Agrawal; Vishwani D. - Murray Hill NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System And Method For Optimizing Fault Coverage Based On Optimized Test Point Insertion Determinations For Logical Circuits App 20210318379 - Millican; Spencer ; et al.	2021-10-14
Method and system for identifying tested path delay faults Grant 6,131,181 - Bushnell , et al. October 10, 2	2000-10-10
Testing and removal of redundancies in VLSI circuits with non-boolean primitives Grant 5,657,240 - Chakradhar , et al. August 12, 1	1997-08-12
Delay testing of high-performance digital components by a slow-speed tester Grant 5,606,567 - Agrawal , et al. February 25, 1	1997-02-25
Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs) Grant 5,499,249 - Agrawal , et al. March 12, 1	1996-03-12
Method for testing delay faults in non-scan sequential circuits Grant 5,365,528 - Agrawal , et al. November 15, 1	1994-11-15
Method and integrated circuit adapted for partial scan testability Grant 5,043,986 - Agrawal , et al. August 27, 1	1991-08-27
Scan testable integrated circuit Grant 4,493,077 - Agrawal , et al. January 8, 1	1985-01-08

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