Agrawal; Om P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Agrawal; Om P..The latest application filed is for "efficiently transmitting bulk data over a mobile network".

Company Profile

0.114.11

Agrawal; Om P. - Saskatoon CA
Agrawal; Om P. - Los Altos CA
Agrawal; Om P - Los Altos CA
Agrawal; Om P. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Efficiently transmitting bulk data over a mobile network Grant 9,648,474 - Agrawal , et al. May 9, 2	2017-05-09
Efficiently Transmitting Bulk Data Over A Mobile Network App 20160094961 - Agrawal; Om P. ; et al.	2016-03-31
Flexible memory architectures for programmable logic devices Grant 7,957,208 - Tang , et al. June 7, 2	2011-06-07
Programmable logic device with a multi-data rate SDRAM interface Grant 7,787,326 - Sharpe-Geisler , et al. August 31, 2	2010-08-31
Programmable logic devices with custom identification systems and methods Grant 7,702,977 - Tang , et al. April 20, 2	2010-04-20
Programmable logic device with multiple slice types Grant 7,696,784 - Agrawal , et al. April 13, 2	2010-04-13
Dual-slice architectures for programmable logic devices Grant 7,675,321 - Agrawal , et al. March 9, 2	2010-03-09
Area efficient routing architectures for programmable logic devices Grant 7,605,606 - Ding , et al. October 20, 2	2009-10-20
Logic block control architectures for programmable logic devices Grant 7,592,834 - Agrawal , et al. September 22, 2	2009-09-22
Programmable logic devices with user non-volatile memory Grant 7,554,358 - Fontana , et al. June 30, 2	2009-06-30
Programmable logic devices with custom identification systems and methods Grant 7,546,498 - Tang , et al. June 9, 2	2009-06-09
Flexible memory architectures for programmable logic devices Grant 7,495,970 - Tang , et al. February 24, 2	2009-02-24
Programmable logic devices with transparent field reconfiguration Grant 7,459,931 - Tang , et al. December 2, 2	2008-12-02
Programmable logic devices with distributed memory Grant 7,459,935 - Agrawal , et al. December 2, 2	2008-12-02
Interface block architectures Grant 7,427,874 - Agrawal , et al. September 23, 2	2008-09-23
Logic block control architectures for programmable logic devices Grant 7,397,276 - Agrawal , et al. July 8, 2	2008-07-08
Dual slice architectures for programmable logic devices Grant 7,385,417 - Agrawal , et al. June 10, 2	2008-06-10
Programmable logic device architecture with multiple slice types Grant 7,378,872 - Agrawal , et al. May 27, 2	2008-05-27
Programmable logic device providing a serial peripheral interface Grant 7,378,873 - Tang , et al. May 27, 2	2008-05-27
Programmable logic devices with distributed memory and non-volatile memory Grant 7,355,441 - Agrawal , et al. April 8, 2	2008-04-08
Programmable logic device with a double data rate SDRAM interface Grant 7,342,838 - Sharpe-Geisler , et al. March 11, 2	2008-03-11
Interface block architectures Grant 7,327,159 - Agrawal , et al. February 5, 2	2008-02-05
SERDES with programmable I/O architecture Grant 7,327,160 - Agrawal , et al. February 5, 2	2008-02-05
Programmable interconnect architecture for programmable logic devices Grant 7,256,613 - Sharpe-Geisler , et al. August 14, 2	2007-08-14
Upgradeable and reconfigurable programmable logic device Grant 7,215,139 - Agrawal , et al. May 8, 2	2007-05-08
SERDES with programmable I/O architecture Grant 7,208,975 - Agrawal , et al. April 24, 2	2007-04-24
FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections Grant RE39,510 - Agrawal , et al. March 13, 2	2007-03-13
Block-oriented architecture for a programmable interconnect circuit Grant 7,154,298 - Agrawal , et al. December 26, 2	2006-12-26
Upgradeable and reconfigurable programmable logic device App 20060232295 - Agrawal; Om P. ; et al.	2006-10-19
Scalable serializer-deserializer architecture and programmable interface Grant 7,098,685 - Agrawal , et al. August 29, 2	2006-08-29
Programmable logic device with flexible memory allocation and routing Grant 7,088,134 - Agrawal , et al. August 8, 2	2006-08-08
Upgradeable and reconfigurable programmable logic device Grant 7,081,771 - Agrawal , et al. July 25, 2	2006-07-25
Clock generator with skew control Grant 7,034,599 - Agrawal , et al. April 25, 2	2006-04-25
FPGA with register-intensive architecture Grant 7,028,281 - Agrawal , et al. April 11, 2	2006-04-11
Clock generator Grant 7,019,577 - Agrawal , et al. March 28, 2	2006-03-28
Hierarchical general interconnect architecture for high density FPGA'S Grant 7,000,212 - Agrawal , et al. February 14, 2	2006-02-14
Upgradeable and reconfigurable programmable logic device App 20050189962 - Agrawal, Om P. ; et al.	2005-09-01
Programmable logic device with enhanced wide and deep logic capability Grant 6,922,078 - Agrawal July 26, 2	2005-07-26
Field programmable gate array having embedded memory with configurable depth and width Grant 6,919,736 - Agrawal , et al. July 19, 2	2005-07-19
Clock generator with skew control Grant 6,885,227 - Agrawal , et al. April 26, 2	2005-04-26
CPLD with multi-function blocks and distributed memory Grant 6,879,182 - Agrawal , et al. April 12, 2	2005-04-12
Multi-stage interconnect architecture for complex programmable logic devices Grant 6,864,713 - Agrawal , et al. March 8, 2	2005-03-08
Cascaded logic block architecture for complex programmable logic devices Grant 6,861,871 - Agrawal , et al. March 1, 2	2005-03-01
High speed interface for a programmable interconnect circuit Grant 6,861,868 - Agrawal , et al. March 1, 2	2005-03-01
Clock generator with skew control App 20050024105 - Agrawal, Om P. ; et al.	2005-02-03
Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation Grant 6,838,904 - Agrawal , et al. January 4, 2	2005-01-04
Non-volatile and reconfigurable programmable logic devices Grant 6,828,823 - Tsui , et al. December 7, 2	2004-12-07
Programmable optimized-distribution logic allocator for a high-density complex PLD Grant 6,753,696 - Agrawal , et al. June 22, 2	2004-06-22
I/O block for a programmable interconnect circuit Grant 6,703,860 - Agrawal , et al. March 9, 2	2004-03-09
Hierarchical general interconnect architecture for high density fpga's App 20040010767 - Agrawal, Om P. ; et al.	2004-01-15
Programmable interconnect circuit with a phase-locked loop Grant 6,661,254 - Agrawal , et al. December 9, 2	2003-12-09
Multi-level routing structure for a programmable interconnect circuit Grant 6,653,861 - Agrawal , et al. November 25, 2	2003-11-25
Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures Grant 6,653,860 - Agrawal , et al. November 25, 2	2003-11-25
Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use Grant 6,650,142 - Agrawal , et al. November 18, 2	2003-11-18
High speed interface for a programmable interconnect circuit Grant 6,650,141 - Agrawal , et al. November 18, 2	2003-11-18
Variable grain architecture for FPGA integrated circuits Grant 6,621,298 - Agrawal , et al. September 16, 2	2003-09-16
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources Grant 6,590,415 - Agrawal , et al. July 8, 2	2003-07-08
High Speed Interface For A Programmable Interconnect Circuit App 20030112031 - Agrawal, Om P. ; et al.	2003-06-19
Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures App 20030107401 - Agrawal, Om P. ; et al.	2003-06-12
Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources Grant 6,526,558 - Agrawal , et al. February 25, 2	2003-02-25
Methods for configuring FPGA ' S having viriable grain components for providing time-shared access to interconnect resources App 20020196809 - Agrawal, Om P. ; et al.	2002-12-26
Variable grain architecture for FPGA integrated circuits App 20020186044 - Agrawal, Om P. ; et al.	2002-12-12
Variable grain architecture for FPGA integrated circuits Grant 6,380,759 - Agrawal , et al. April 30, 2	2002-04-30
Scalable architecture for high density CPLD's having two-level hierarchy of routing resources Grant 6,348,813 - Agrawal , et al. February 19, 2	2002-02-19
Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources App 20010056570 - Agrawal, Om P. ; et al.	2001-12-27
Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits Grant 6,275,064 - Agrawal , et al. August 14, 2	2001-08-14
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources Grant 6,249,144 - Agrawal , et al. June 19, 2	2001-06-19
FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks Grant 6,216,257 - Agrawal , et al. April 10, 2	2001-04-10
FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections Grant 6,211,695 - Agrawal , et al. April 3, 2	2001-04-03
Enhanced I/O control flexibility for generating control signals Grant 6,191,612 - Agrawal , et al. February 20, 2	2001-02-20
Scalable architecture for high density CPLDS having two-level hierarchy of routing resources Grant 6,184,713 - Agrawal , et al. February 6, 2	2001-02-06
FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals Grant 6,181,163 - Agrawal , et al. January 30, 2	2001-01-30
Efficient interconnect network for use in FPGA device having variable grain architecture Grant 6,163,168 - Nguyen , et al. December 19, 2	2000-12-19
Tileable and compact layout for super variable grain blocks within FPGA device Grant 6,154,051 - Nguyen , et al. November 28, 2	2000-11-28
Enhanced macrocell module for high density CPLD architectures Grant 6,150,841 - Agrawal , et al. November 21, 2	2000-11-21
Dual port SRAM memory for run time use in FPGA integrated circuits Grant 6,127,843 - Agrawal , et al. October 3, 2	2000-10-03
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources Grant 6,124,730 - Agrawal , et al. September 26, 2	2000-09-26
Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits Grant 6,107,823 - Agrawal , et al. August 22, 2	2000-08-22
Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's Grant 6,102,963 - Agrawal August 15, 2	2000-08-15
Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources Grant 6,100,715 - Agrawal , et al. August 8, 2	2000-08-08
Variable grain architecture for FPGA integrated circuits Grant 6,097,212 - Agrawal , et al. August 1, 2	2000-08-01
FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode Grant 6,081,473 - Agrawal , et al. June 27, 2	2000-06-27
Programmable input/output block (IOB) in FPGA integrated circuits Grant 6,034,544 - Agrawal , et al. March 7, 2	2000-03-07
Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits Grant 5,990,702 - Agrawal , et al. November 23, 1	1999-11-23
Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits Grant 5,982,193 - Agrawal , et al. November 9, 1	1999-11-09
Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices Grant 5,818,254 - Agrawal , et al. October 6, 1	1998-10-06
Flexible synchronous/asynchronous cell structure for a high density programmable logic device Grant 5,811,986 - Agrawal , et al. September 22, 1	1998-09-22
Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device Grant 5,789,939 - Agrawal , et al. August 4, 1	1998-08-04
Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD Grant 5,781,030 - Agrawal , et al. July 14, 1	1998-07-14
Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses Grant 5,644,496 - Agrawal , et al. July 1, 1	1997-07-01
Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses Grant 5,621,650 - Agrawal , et al. April 15, 1	1997-04-15
Multiple array programmable logic device with a plurality of programmable switch matrices Grant 5,617,042 - Agrawal April 1, 1	1997-04-01
Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer Grant 5,587,921 - Agrawal , et al. December 24, 1	1996-12-24
Array of configurable logic blocks including cascadable lookup tables Grant 5,586,044 - Agrawal , et al. December 17, 1	1996-12-17
Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation Grant 5,521,529 - Agrawal , et al. May 28, 1	1996-05-28
Flexible synchronous/asynchronous cell structure for a high density programmable logic device Grant 5,489,857 - Agrawal , et al. February 6, 1	1996-02-06
Constant delay interconnect for coupling configurable logic blocks Grant 5,490,074 - Agrawal , et al. February 6, 1	1996-02-06
Logic allocator for a programmable logic device Grant 5,485,104 - Agrawal , et al. January 16, 1	1996-01-16
Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output Grant 5,469,368 - Agrawal , et al. November 21, 1	1995-11-21
Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices Grant 5,457,409 - Agrawal , et al. October 10, 1	1995-10-10
High speed centralized switch matrix for a programmable logic device Grant 5,436,514 - Agrawal , et al. * July 25, 1	1995-07-25
Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix Grant 5,426,335 - Agrawal , et al. June 20, 1	1995-06-20
Programmable gate array device having cascaded means for function definition Grant 5,422,823 - Agrawal , et al. June 6, 1	1995-06-06
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block Grant 5,359,536 - Agrawal , et al. October 25, 1	1994-10-25
Integrated circuit programmable sequencing element apparatus Grant 5,349,670 - Agrawal , et al. September 20, 1	1994-09-20
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block Grant 5,329,460 - Agrawal , et al. July 12, 1	1994-07-12
Programmable, expandable controller with flexible I/O Grant 5,261,116 - Agrawal November 9, 1	1993-11-09
Programmable gate array with improved configurable logic block Grant 5,260,881 - Agrawal , et al. November 9, 1	1993-11-09
Interconnect structure for programmable logic device Grant 5,255,203 - Agrawal , et al. October 19, 1	1993-10-19
PLDs with high drive capability Grant 5,247,195 - Turner , et al. September 21, 1	1993-09-21
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block Grant 5,233,539 - Agrawal , et al. August 3, 1	1993-08-03
Programmable gate array with logic cells having symmetrical input/output structures Grant 5,231,588 - Agrawal , et al. July 27, 1	1993-07-27
Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix Grant 5,225,719 - Agrawal , et al. * July 6, 1	1993-07-06
Programmable gate array with improved interconnect structure Grant 5,212,652 - Agrawal , et al. May 18, 1	1993-05-18
Programmable logic device incorporating digital-to-analog converter Grant 5,191,242 - Agrawal , et al. March 2, 1	1993-03-02
Programmable gate array with logic cells having configurable output enable Grant 5,185,706 - Agrawal , et al. February 9, 1	1993-02-09
Programmable logic device with observability and preloadability for buried state registers Grant 5,168,177 - Shankar , et al. * December 1, 1	1992-12-01
Programmable logic device incorporating voltage comparator Grant 5,153,462 - Agrawal , et al. October 6, 1	1992-10-06
Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix Grant 5,151,623 - Agrawal September 29, 1	1992-09-29
Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions Grant 5,027,315 - Agrawal , et al. June 25, 1	1991-06-25
Multiple array high performance programmable logic device family Grant 5,015,884 - Agrawal , et al. May 14, 1	1991-05-14
Flexible, programmable cell array interconnected by a programmable switch matrix Grant 4,963,768 - Agrawal , et al. October 16, 1	1990-10-16
Prom with programmable output structures Grant 4,779,229 - Agrawal October 18, 1	1988-10-18