Patent | Date |
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Relaxed low-defect SGOI for strained SI CMOS applications Grant 8,227,792 - Agnello , et al. July 24, 2 | 2012-07-24 |
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Grant 7,683,434 - Agnello , et al. March 23, 2 | 2010-03-23 |
Preventing Cavitation In High Aspect Ratio Dielectric Regions Of Semiconductor Device App 20080303070 - Agnello; Paul D. ;   et al. | 2008-12-11 |
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Grant 7,459,384 - Agnello , et al. December 2, 2 | 2008-12-02 |
RELAXED LOW-DEFECT SGOI FOR STRAINED Si CMOS APPLICATIONS App 20080135875 - Agnello; Paul D. ;   et al. | 2008-06-12 |
Method of fabricating semiconductor side wall fin Grant 7,361,556 - Adkisson , et al. April 22, 2 | 2008-04-22 |
Relaxed, low-defect SGOI for strained Si CMOS applications Grant 7,358,166 - Agnello , et al. April 15, 2 | 2008-04-15 |
Method of fabricating semiconductor side wall fin Grant 7,265,417 - Adkisson , et al. September 4, 2 | 2007-09-04 |
Method of fabricating semiconductor side wall fin App 20070026617 - Adkisson; James W. ;   et al. | 2007-02-01 |
Method of fabricating semiconductor side wall fin Grant 7,163,864 - Adkisson , et al. January 16, 2 | 2007-01-16 |
Double gate trench transistor Grant 7,112,845 - Adkisson , et al. September 26, 2 | 2006-09-26 |
Relaxed, low-defect SGOI for strained Si CMOS applications App 20060030133 - Agnello; Paul D. ;   et al. | 2006-02-09 |
Preventing Cavitation In High Aspect Ratio Dielectric Regions Of Semiconductor Device App 20050287798 - Agnello, Paul D. ;   et al. | 2005-12-29 |
Relaxed, low-defect SGOI for strained Si CMOS applications Grant 6,946,373 - Agnello , et al. September 20, 2 | 2005-09-20 |
Salicide formation method Grant 6,916,729 - Fang , et al. July 12, 2 | 2005-07-12 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture Grant 6,891,228 - Park , et al. May 10, 2 | 2005-05-10 |
Method To Produce Transistor Having Reduced Gate Height App 20050048732 - Park, Heemyoung ;   et al. | 2005-03-03 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture App 20050040465 - Park, Heemyong ;   et al. | 2005-02-24 |
Method of fabricating semiconductor side wall fin App 20050001216 - Adkisson, James W. ;   et al. | 2005-01-06 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture Grant 6,828,630 - Park , et al. December 7, 2 | 2004-12-07 |
Salicide formation method App 20040203229 - Fang, Sunfei ;   et al. | 2004-10-14 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture App 20040129979 - Park, Heemyong ;   et al. | 2004-07-08 |
Relaxed, low-defect SGOI for strained Si CMOS applications App 20040094763 - Agnello, Paul D. ;   et al. | 2004-05-20 |
Semiconductor chip having both compact memory and high performance logic Grant 6,686,617 - Agnello , et al. February 3, 2 | 2004-02-03 |
Partially Removable Spacer With Salicide Formation App 20030042551 - AGNELLO, PAUL D. ;   et al. | 2003-03-06 |
Double gate trench transistor Grant 6,472,258 - Adkisson , et al. October 29, 2 | 2002-10-29 |
Double gate trench transistor App 20020140039 - Adkisson, James W. ;   et al. | 2002-10-03 |
Structures and methods to minimize plasma charging damage in silicon on insulator devices App 20020142526 - Khare, Mukesh ;   et al. | 2002-10-03 |
Vertical trench-formed dual-gate FET device structure and method for creation Grant 6,406,962 - Agnello , et al. June 18, 2 | 2002-06-18 |
Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap App 20020025639 - Agnello, Paul D. ;   et al. | 2002-02-28 |
Plasma treatment to enhance inorganic dielectric adhesion to copper App 20010053591 - Buchwalter, Leena P. ;   et al. | 2001-12-20 |
Semiconductor chip having both compact memory and high performance logic App 20010031535 - Agnello, Paul D. ;   et al. | 2001-10-18 |
Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap Grant 6,274,446 - Agnello , et al. August 14, 2 | 2001-08-14 |
Plasma treatment to enhance inorganic dielectric adhesion to copper Grant 6,261,951 - Buchwalter , et al. July 17, 2 | 2001-07-17 |
Plasma treatment to enhance inorganic dielectric adhesion to copper Grant 6,255,217 - Agnello , et al. July 3, 2 | 2001-07-03 |
Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen Grant 5,624,869 - Agnello , et al. April 29, 1 | 1997-04-29 |
Tasin oxygen diffusion barrier in multilayer structures Grant 5,576,579 - Agnello , et al. November 19, 1 | 1996-11-19 |
Comprehensive process for low temperature epitaxial growth Grant 5,378,651 - Agnello , et al. January 3, 1 | 1995-01-03 |