Adler; Steven J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Adler; Steven J..The latest application filed is for "trench dmos transistor with reduced gate-to-drain capacitance".

Company Profile

0.14.4

Adler; Steven J. - Plano TX
Adler; Steven J. - Saratoga CA US
Adler; Steven J. - Cape Elizabeth ME
Adler; Steven J. - Tempe AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Trench DMOS transistor with reduced gate-to-drain capacitance Grant 10,741,687 - Leng , et al. A	2020-08-11
Trench Dmos Transistor With Reduced Gate-to-drain Capacitance App 20170309743 - Leng; Yaojian ; et al.	2017-10-26
Trench DMOS transistor with reduced gate-to-drain capacitance Grant 9,716,167 - Leng , et al. July 25, 2	2017-07-25
Integration of structurally-stable isolated capacitive micromachined ultrasonic transducer (CMUT) array cells and array elements Grant 8,563,345 - Adler , et al. October 22, 2	2013-10-22
Integration Of Vertical Bjt Or Hbt Into Soi Technology App 20130001647 - Adler; Steven J.	2013-01-03
Method of forming a capacitive micromachined ultrasonic transducer (CMUT) Grant 8,324,006 - Adler , et al. December 4, 2	2012-12-04
Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance App 20120211826 - Leng; Yaojian ; et al.	2012-08-23
Integration Of Structurally-stable Isolated Capacitive Micromachined Ultrasonic Transducer (cmut) Array Cells And Array Elements App 20120187508 - Adler; Steven J. ; et al.	2012-07-26
System and method for providing a self aligned bipolar transistor using a silicon nitride ring Grant 7,927,958 - Xu , et al. April 19, 2	2011-04-19
System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter Grant 7,910,447 - Xu , et al. March 22, 2	2011-03-22
System and method for using siliciding PECVD silicon nitride as a dielectric anti-reflective coating and hard mask Grant 7,884,023 - McCulloh , et al. February 8, 2	2011-02-08
System and method for providing a single deposition emitter/base in a bipolar junction transistor Grant 7,781,295 - Ramdani , et al. August 24, 2	2010-08-24
System and method for manufacturing an emitter structure in a complementary bipolar CMOS transistor manufacturing process Grant 7,678,657 - Thibeault , et al. March 16, 2	2010-03-16
System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base Grant 7,642,168 - Xu , et al. January 5, 2	2010-01-05
Double implanted laterally diffused MOS device and method thereof Grant 5,371,394 - Ma , et al. December 6, 1	1994-12-06
Low on resistance field effect transistor Grant 5,252,848 - Adler , et al. October 12, 1	1993-10-12

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