ACKMANN; Paul

Patent Applications and Registrations

Patent applications and USPTO patent grants for ACKMANN; Paul.The latest application filed is for "gap fill void and connection structures".

Company Profile

2.28.29

ACKMANN; Paul - Gansevoort NY
Ackmann; Paul - Ganesvoort NY
Ackmann; Paul - Buda TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Gap Fill Void And Connection Structures App 20210134658 - HUANG; Haigou ; et al.	2021-05-06
Gap fill void and connection structures Grant 10,923,388 - Huang , et al. February 16, 2	2021-02-16
Gap Fill Void And Connection Structures App 20200235002 - HUANG; Haigou ; et al.	2020-07-23
Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device Grant 10,002,827 - Ning , et al. June 19, 2	2018-06-19
Metrology pattern layout and method of use thereof Grant 9,864,831 - Ning , et al. January 9, 2	2018-01-09
Method wherein test cells and dummy cells are included into a layout of an integrated circuit Grant 9,817,940 - Ueberreiter , et al. November 14, 2	2017-11-14
Cross technology reticle (CTR) or multi-layer reticle (MLR) CDU, registration, and overlay techniques Grant 9,798,238 - Ning , et al. October 24, 2	2017-10-24
Monitoring pattern for devices Grant 9,791,772 - Ning , et al. October 17, 2	2017-10-17
Method Wherein Test Cells And Dummy Cells Are Included Into A Layout Of An Integrated Circuit App 20170235866 - Ueberreiter; Guido ; et al.	2017-08-17
Method For Selective Re-routing Of Selected Areas In A Target Layer And In Adjacent Interconnecting Layers Of An Ic Device App 20170186687 - NING; Guoxiang ; et al.	2017-06-29
Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device Grant 9,672,313 - Ning , et al. June 6, 2	2017-06-06
Method wherein test cells and dummy cells are included into a layout of an integrated circuit Grant 9,672,312 - Ueberreiter , et al. June 6, 2	2017-06-06
Semiconductor device resolution enhancement by etching multiple sides of a mask Grant 9,658,531 - Ning , et al. May 23, 2	2017-05-23
Multiple threshold convergent OPC model Grant 9,645,486 - Lim , et al. May 9, 2	2017-05-09
Reticle, system comprising a plurality of reticles and method for the formation thereof Grant 9,535,319 - Ueberreiter , et al. January 3, 2	2017-01-03
Pattern Classification Based Proximity Corrections For Reticle Fabrication App 20160363853 - NING; Guoxiang ; et al.	2016-12-15
Pattern classification based proximity corrections for reticle fabrication Grant 9,500,945 - Ning , et al. November 22, 2	2016-11-22
Method Wherein Test Cells And Dummy Cells Are Included Into A Layout Of An Integrated Circuit App 20160328510 - Ueberreiter; Guido ; et al.	2016-11-10
Method For Selective Re-routing Of Selected Areas In A Target Layer And In Adjacent Interconnecting Layers Of An Ic Device App 20160328511 - NING; Guoxiang ; et al.	2016-11-10
Reticle, System Comprising A Plurality Of Reticles And Method For The Formation Thereof App 20160291457 - Ueberreiter; Guido ; et al.	2016-10-06
Metrology Pattern Layout And Method Of Use Thereof App 20160196381 - NING; Guoxiang ; et al.	2016-07-07
Mask error compensation by optical modeling calibration Grant 9,384,318 - Ning , et al. July 5, 2	2016-07-05
Cross Technology Reticle (ctr) Or Multi-layer Reticle (mlr) Cdu, Registration, And Overlay Techniques App 20160179006 - NING; Guo Xiang ; et al.	2016-06-23
Overlay mark dependent dummy fill to mitigate gate height variation Grant 9,368,453 - Ning , et al. June 14, 2	2016-06-14
Multiple Threshold Convergent Opc Model App 20160161840 - LIM; Chin Teong ; et al.	2016-06-09
Cross technology reticle (CTR) or multi-layer reticle (MLR) CDU, registration, and overlay techniques Grant 9,341,961 - Ning , et al. May 17, 2	2016-05-17
Metrology pattern layout and method of use thereof Grant 9,323,882 - Ning , et al. April 26, 2	2016-04-26
Overlay Mark Dependent Dummy Fill To Mitigate Gate Height Variation App 20160079180 - NING; Guoxiang ; et al.	2016-03-17
Efficient optical proximity correction repair flow method and apparatus Grant 9,250,538 - Ning , et al. February 2, 2	2016-02-02
Overlay mark dependent dummy fill to mitigate gate height variation Grant 9,252,061 - Ning , et al. February 2, 2	2016-02-02
Customized alleviation of stresses generated by through-substrate via(S) Grant 9,236,301 - Ning , et al. January 12, 2	2016-01-12
Mask Error Compensation By Optical Modeling Calibration App 20150310157 - NING; Guoxiang ; et al.	2015-10-29
Overlay Mark Dependent Dummy Fill To Mitigate Gate Height Variation App 20150287651 - NING; Guoxiang ; et al.	2015-10-08
Metrology Pattern Layout And Method Of Use Thereof App 20150278426 - NING; Guoxiang ; et al.	2015-10-01
Forming alignment mark and resulting mark Grant 9,136,223 - Ning , et al. September 15, 2	2015-09-15
Layout For Reticle And Wafer Scanning Electron Microscope Registration Or Overlay Measurements App 20150221565 - NING; Guo Xiang ; et al.	2015-08-06
Efficient Optical Proximity Correction Repair Flow Method And Apparatus App 20150192866 - NING; Guoxiang ; et al.	2015-07-09
Layout for reticle and wafer scanning electron microscope registration or overlay measurements Grant 9,029,855 - Ning , et al. May 12, 2	2015-05-12
Device Layout For Reducing Through-silicon-via Stress App 20150028482 - Ning; Guoxiang ; et al.	2015-01-29
Forming Alignment Mark And Resulting Mark App 20150028500 - NING; Guoxiang ; et al.	2015-01-29
Customized Alleviation Of Stresses Generated By Through-substrate Via(s) App 20150017803 - NING; Guoxiang ; et al.	2015-01-15
Optical Proximity Correction For Connecting Via Between Layers Of A Device App 20150006138 - Ning; Guo Xiang ; et al.	2015-01-01
Semiconductor Device Resolution Enhancement By Etching Multiple Sides Of A Mask App 20140370447 - NING; Guoxiang ; et al.	2014-12-18
Circuit structures and methods of fabrication with enhanced contact via electrical connection Grant 8,907,496 - Ning , et al. December 9, 2	2014-12-09
Circuit Structures And Methods Of Fabrication With Enhanced Contact Via Electrical Connection App 20140353843 - NING; GuoXiang ; et al.	2014-12-04
Semiconductor device resolution enhancement by etching multiple sides of a mask Grant 8,895,211 - Ning , et al. November 25, 2	2014-11-25
Cross Technology Reticle (ctr) Or Multi-layer Reticle (mlr) Cdu, Registration, And Overlay Techniques App 20140268090 - NING; Guo Xiang ; et al.	2014-09-18
Monitoring Pattern For Devices App 20140273310 - NING; Guoxiang ; et al.	2014-09-18
Layout For Reticle And Wafer Scanning Electron Microscope Registration Or Overlay Measurements App 20140264334 - NING; Guo Xiang ; et al.	2014-09-18
Semiconductor Device Resolution Enhancement By Etching Multiple Sides Of A Mask App 20140162176 - NING; Guoxiang ; et al.	2014-06-12
Method and apparatus for programmed latency for improving wafer-to-wafer uniformity Grant 6,405,144 - Toprac , et al. June 11, 2	2002-06-11
Automated data management system for analysis and control of photolithography stepper performance Grant 5,757,673 - Osheiski , et al. May 26, 1	1998-05-26
Automated data management system for analysis and control of photolithography stepper performance Grant 5,586,059 - Oshelski , et al. December 17, 1	1996-12-17

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