Achanta; Janardhan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Achanta; Janardhan.The latest application filed is for "apparatus and methods for compensating for variations in fabrication process of component(s) in a memory".
- Achanta; Janardhan - Bengaluru IN
- Achanta; Janardhan - Kakinada IN
| Patent | Date |
|---|---|
| Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory Grant 10,998,018 - Ranjan , et al. May 4, 2 | 2021-05-04 |
| Apparatus And Methods For Compensating For Variations In Fabrication Process Of Component(s) In A Memory App 20210110854 - RANJAN; Shubham ; et al. | 2021-04-15 |
| Reducing the load on the bitlines of a ROM bitcell array Grant 9,898,568 - Srivastava , et al. February 20, 2 | 2018-02-20 |
| Using a cut mask to form spaces representing spacing violations in a semiconductor structure Grant 9,710,589 - Dave , et al. July 18, 2 | 2017-07-18 |
| Reducing The Load On The Bitlines Of A Rom Bitcell Array App 20160378898 - Srivastava; Naveen Chandra ; et al. | 2016-12-29 |
| Semiconductor Area Optimization App 20160378899 - Dave; Kalpeshkumar Girishchandra ; et al. | 2016-12-29 |
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