Abercrombie; David A.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Abercrombie; David A..The latest application filed is for "semiconductor layout context around a point of interest".
- Abercrombie; David A. - Apex NC
- Abercrombie; David A. - Sherwood OR US
- Abercrombie; David A. - Gresham OR
- Abercrombie; David A. - Cedar Park TX
| Patent | Date |
|---|---|
| Semiconductor Layout Context Around A Point Of Interest App 20220309222 - Abercrombie; David A. ; et al. | 2022-09-29 |
| Simultaneous multi-layer fill generation Grant 10,552,565 - Anikin , et al. Fe | 2020-02-04 |
| Simultaneous Multi-Layer Fill Generation App 20170147732 - Anikin; Eugene ; et al. | 2017-05-25 |
| Simultaneous multi-layer fill generation Grant 9,652,574 - Anikin , et al. May 16, 2 | 2017-05-16 |
| Model-based design verification Grant 8,612,919 - Pikus , et al. December 17, 2 | 2013-12-17 |
| Simultaneous Multi-Layer Fill Generation App 20110289471 - Anikin; Eugene ; et al. | 2011-11-24 |
| Yield profile manipulator Grant 7,930,655 - Desu , et al. April 19, 2 | 2011-04-19 |
| Simultaneous Multi-Layer Fill Generation App 20090077506 - Anikin; Eugene ; et al. | 2009-03-19 |
| Yield Profile Manipulator App 20080216048 - Desu; ChandraSekhar ; et al. | 2008-09-04 |
| Model-based design verification App 20080189667 - Pikus; Fedor G. ; et al. | 2008-08-07 |
| Yield profile manipulator Grant 7,395,522 - Desu , et al. July 1, 2 | 2008-07-01 |
| Pattern component analysis and manipulation Grant 7,137,098 - Whitefield , et al. November 14, 2 | 2006-11-14 |
| Parametric outlier detection Grant 7,062,415 - Whitefield , et al. June 13, 2 | 2006-06-13 |
| Substrate profile analysis Grant 7,039,556 - Whitefield , et al. May 2, 2 | 2006-05-02 |
| Pattern component analysis and manipulation App 20060059452 - Whitefield; Bruce J. ; et al. | 2006-03-16 |
| Substrate profile analysis App 20050288896 - Whitefield, Bruce J. ; et al. | 2005-12-29 |
| Yield profile manipulator App 20050229144 - Desu, Chandra Sekhar ; et al. | 2005-10-13 |
| Heaviest only fail potential Grant 6,658,361 - Rehani , et al. December 2, 2 | 2003-12-02 |
| Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits Grant 5,937,324 - Abercrombie , et al. August 10, 1 | 1999-08-10 |
| Semiconductor component with multi-level interconnect system and method of manufacture Grant 5,798,568 - Abercrombie , et al. August 25, 1 | 1998-08-25 |
| Method and apparatus for testing an integrated circuit Grant 5,666,063 - Abercrombie , et al. September 9, 1 | 1997-09-09 |
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