Mark For: NNMAX™ trademark registration is intended to cover the categories of integrated circuit (IP) cores implementing embedded field programmable gate arrays (FPGAs) with clusters of multiplier-accumulators (MACs) optimized for neural network inference; downloadable software for programming the embedded field programmable gate array (FPGA) integrated circuit (IP) cores using neural network description models; instructional documentation and user guides, sold as a unit, for use with the foregoing. [all]
Status
2020-05-07 UTC
LIVE APPLICATION Published for Opposition
A pending trademark application has been examined by the Office and has been published in a way that provides an opportunity for the public to oppose its registration.
(Electrical and scientific apparatus) Scientific, nautical, surveying, electric, photographic, cinematographic, optical, weighing, measuring, signaling, checking (supervision), lifesaving and teaching apparatus and instruments; apparatus for recording, transmission or reproduction of sound or images; magnetic data carriers, recording discs; automatic vending machines and mechanisms for coin operated apparatus; cash registers, calculating machines, data processing equipment and computers; fire-extinguishing apparatus.
Filed Use
Yes
Current Use
No
Intent To Use
Yes
Filed ITU
No
44D Filed
No
44E Current
No
66A Current
No
Current Basis
No
No Basis
No
Attorney Name
Jessica L. Rothstein
Attorney Docket Number
136394261006
Law Office Assigned
N30
Employee Name
BEDNARZ, DUSTIN THOMAS
Timeline
2019-03-00
Date of First Use
2019-05-09
Application Filed
2019-07-19
Location: TMO LAW OFFICE 121 - EXAMINING ATTORNEY ASSIGNED
2019-07-19
Status: Live/Pending
2019-07-19
Transaction Date
2020-02-25
Published
2020-04-21
Location: INTENT TO USE SECTION
2020-04-21
Status: Notice of Allowance (NOA) sent (issued) to the applicant. Applicant must file a Statement of Use or Extension Request within six
JESSICA L. ROTHSTEIN GOODWIN PROCTER LLP 620 EIGHTH AVENUE THE NEW YORK TIMES BUILDING NEW YORK, NY 10018
Good, Services, and Codes
IC 009. US 021 023 026 036 038. G & S: Integrated circuit (IP) cores implementing embedded field programmable gate arrays (FPGAs) with clusters of multiplier-accumulators (MACs) optimized for neural network inference; downloadable software for programming the embedded field programmable gate array (FPGA) integrated circuit (IP) cores using neural network description models; instructional documentation and user guides, sold as a unit, for use with the foregoing
International Codes:
9
U.S. Codes:
021,023,026,036,038
Type Code
Type
GS0091
Integrated circuit (IP) cores implementing embedded field programmable gate arrays (FPGAs) with clusters of multiplier-accumulators (MACs) optimized for neural network inference; software for programming the embedded FPGA IP core using neural network description models; documentation and user guides, sold as a unit, for use with the foregoing
Trademark Filing History
Description
Date
Proceeding Number
NOA E-MAILED - SOU REQUIRED FROM APPLICANT
2020-04-21
PUBLISHED FOR OPPOSITION
2020-02-25
OFFICIAL GAZETTE PUBLICATION CONFIRMATION E-MAILED
2020-02-25
NOTIFICATION OF NOTICE OF PUBLICATION E-MAILED
2020-02-05
TEAS/EMAIL CORRESPONDENCE ENTERED
2020-01-22
70138
CORRESPONDENCE RECEIVED IN LAW OFFICE
2020-01-22
70138
APPROVED FOR PUB - PRINCIPAL REGISTER
2020-01-22
ASSIGNED TO LIE
2020-01-20
70138
TEAS RESPONSE TO OFFICE ACTION RECEIVED
2020-01-07
NOTIFICATION OF NON-FINAL ACTION E-MAILED
2019-07-19
6325
NON-FINAL ACTION WRITTEN
2019-07-19
92823
NON-FINAL ACTION E-MAILED
2019-07-19
6325
ASSIGNED TO EXAMINER
2019-07-15
92823
NEW APPLICATION OFFICE SUPPLIED DATA ENTERED IN TRAM
2019-05-29
NEW APPLICATION ENTERED IN TRAM
2019-05-13
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