PINPLAN

NEC Electronics Corporation

Application Filed: 2005-02-23

Trademark Application Details

Mark For: PINPLAN™ trademark registration is intended to cover the categories of electronic and electrical tools and software to test and analyze software and hardware components, namely debuggers, in-circuit emulators, analyzers, stimulators and monitors; computer programs for use in planning, analyzing and checking arrangement of terminals and pins of integrated circuits. [all]

Status

2022-05-07 UTC

DEAD APPLICATION Refused Dismissed or Invalidated

This trademark application was refused, dismissed, or invalidated by the Office and this application is no longer active.

Research	OneLook Acronym Finder
Serial Number	76631561
Mark Literal Elements	PINPLAN
Mark Drawing Type	4 - STANDARD CHARACTER MARK
Mark Type	TRADEMARK
Register	PRINCIPAL
Current Location	INTENT TO USE SECTION 2006-02-07
Basis	1(b)
Class Status	ACTIVE
Primary US Classes	021: Electrical Apparatus, Machines and Supplies 023: Cutlery, Machinery, Tools and Parts Thereof 026: Measuring and Scientific Appliances 036: Musical Instruments and Supplies 038: Prints and Publications
Primary International Class	009 - Primary Class (Electrical and scientific apparatus) Scientific, nautical, surveying, electric, photographic, cinematographic, optical, weighing, measuring, signaling, checking (supervision), lifesaving and teaching apparatus and instruments; apparatus for recording, transmission or reproduction of sound or images; magnetic data carriers, recording discs; automatic vending machines and mechanisms for coin operated apparatus; cash registers, calculating machines, data processing equipment and computers; fire-extinguishing apparatus.
Filed Use	No
Current Use	No
Intent To Use	Yes
Filed ITU	Yes
44D Filed	No
44E Current	No
66A Current	No
Current Basis	No
No Basis	No
Domestic Representative	Morgan, Lewis & Bockius LLP
Attorney Name	Vincent A. Sireci
Attorney Docket Number	056062-5183-
Law Office Assigned	M70
Employee Name	AWRICH, ELLEN

Timeline

2005-02-23	Application Filed
2005-11-15	Published
2005-11-15	Published for Opposition
2006-02-07	Location: INTENT TO USE SECTION
2007-08-08	Abandon
2007-08-08	Status: Abandoned because no Statement of Use or Extension Request timely filed after Notice of Allowance was issued. To view all docume
2007-08-08	Status: Dead/Abandoned
2018-07-08	Transaction Date

Trademark Parties (Applicants & Owners)

Party:	NEC Electronics Corporation
Address	1753, Shimonumabe, Nakahara-ku Kawasaki Kanagawa JAPAN
Legal Entity Type	Corporation
Legal Entity State	JAPAN

Documents

Application	IMAGE/TIFF	2005-02-23
Drawing	IMAGE/TIFF	2005-02-23
Filing Receipt Trademark Application	APPLICATION/XML	2005-03-11
Examiners Amendment		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
XSearch Search Summary		2005-09-19
Notice of Publication	APPLICATION/XML	2005-10-26
Notice of Allowance	APPLICATION/XML	2006-02-07
Extension of Time to File SOU		2006-07-24
Specimen		2006-07-24
ITU Extension Approval		2006-07-26
Extension of Time to File SOU		2007-02-01
Specimen		2007-02-01
ITU Extension Approval		2007-02-03
Notice of Abandonment		2007-12-07
ITU Unit Action		2007-12-08

Attorney of Record

ATTN.: TMSU
MORGAN, LEWIS & BOCKIUS LLP
1111 PENNSYLVANIA AVE NW
WASHINGTON, DC 20004-2541

Good, Services, and Codes

(ABANDONED)
IC 009. US 021 023 026 036 038. G & S: ELECTRON
IC AND ELECTRICAL TOOLS AND SOFTWARE TO TEST AND ANALYZE SOFTWARE AND HARDWARE COMPONENTS, NAMELY DEBUGGERS, IN-CIRCUIT EMULATORS, ANALYZERS, STIMULATORS AND MONITORS; COMPUTER PROGRAMS FOR USE IN PLANNING, ANALYZING AND CHECKING ARRANGEMENT OF TERMINALS AND PINS OF INTEGRATED CIRCUITS

International Codes:	9
U.S. Codes:	021,023,026,036,038

Type Code	Type
GS0091	ELECTRONIC AND ELECTRICAL TOOLS AND SOFTWARE TO TEST AND ANALYZE SOFTWARE AND HARDWARE COMPONENTS, NAMELY DEBUGGERS, IN-CIRCUIT EMULATORS, ANALYZERS, STIMULATORS AND MONITORS; COMPUTER PROGRAMS FOR USE IN PLANNING, ANALYZING AND CHECKING ARRANGEMENT OF TERMINALS AND PINS OF INTEGRATED CIRCUITS

Trademark Filing History

Description	Date	Proceeding Number
ABANDONMENT NOTICE MAILED - NO USE STATEMENT FILED	2007-12-07
ABANDONMENT - NO USE STATEMENT FILED	2007-12-07	48494
TEAS EXTENSION RECEIVED	2007-02-01
SOU EXTENSION 2 GRANTED	2007-02-01	98765
SOU EXTENSION 2 FILED	2007-02-01	98765
TEAS EXTENSION RECEIVED	2006-07-24
SOU EXTENSION 1 GRANTED	2006-07-24	98765
SOU EXTENSION 1 FILED	2006-07-24	98765
NOA MAILED - SOU REQUIRED FROM APPLICANT	2006-02-07
PUBLISHED FOR OPPOSITION	2005-11-15
NOTICE OF PUBLICATION	2005-10-26
LAW OFFICE PUBLICATION REVIEW COMPLETED	2005-09-27	68171
ASSIGNED TO LIE	2005-09-23	68171
EXAMINERS AMENDMENT -WRITTEN	2005-09-19	70703
EXAMINER'S AMENDMENT MAILED	2005-09-19
ASSIGNED TO EXAMINER	2005-09-19	70703
APPROVED FOR PUB - PRINCIPAL REGISTER	2005-09-19
NEW APPLICATION ENTERED IN TRAM	2005-03-07

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